1. Field of the Invention
The invention relates generally to a phase-lock loop (PLL) circuit, and more particularly to reducing jitter in a PLL operating at high frequencies.
2. Description of the Related Art
A phase-lock loop (PLL) is typically used to synchronize (xe2x80x98lockxe2x80x99) an internal voltage-controlled oscillator (VCO) to an external reference signal. A PLL thus keeps a circuit operating at a specific frequency, and is used in a wide variety of electronic circuits for this purpose.
One of the key components of a PLL is a phase-frequency detector (PFD) circuit, which compares the VCO signal to the reference signal and generates a phase error signal that is a measure of their phase difference. The VCO generates a periodic signal with a frequency that is controlled by the phase error signal. The VCO output is coupled to the feedback input of the PFD, thereby forming a feedback loop. If the frequency of the feedback signal is not equal to the frequency of the reference signal, the phase error signal causes the VCO frequency to shift toward the frequency of the reference signal, until the VCO finally locks onto the frequency of the reference.
For very small phase differences, for example when the PLL is in a steady-state condition, the dead zone is the region in which the phase error signal is insensitive to phase-difference changes. Thus one problem with a PFD is that jitter is introduced into the loop due to the dead zone. Most approaches to minimizing the dead zone are particularly complicated, and do not allow the PFD to operate at high frequencies with zero dead zone.
Therefore, there is a need for a phase/frequency detector that operates in high frequency circuits with zero dead zone.
The present invention provides a method and an apparatus for generating a phase error signal from a reference signal and a feedback signal using a modified reset generation mechanism. An input circuit receives a reference signal and a feedback signal. A phase error detector circuit generates a phase error signal based on the reference signal and feedback signal. The input circuit is reset and, after a delay, the phase error detector circuit is reset. The delay is selected so that there is no jitter associated with the dead zone.